
Accelerate. Integrate. Interface. 10-100x High Performance Computing
For many high performance applications the alternative to the multicore rack is to use an accelerator assist to each multicore node. There are a number of instances of these accelerators: GPGPU, Specialized processors (i.e. IBM’s Cell) and FPGAs.
At Maxeler we’ve found that the FPGA array technology wins out on performance for most relevant applications. Given the initial area-time-power disadvantage of the FPGA in (say) a custom designed adder this is a surprising result. The sheer magnitude of the available FPGA parallelism overcomes the initial disadvantage.
Details of event:
Stanford EE Computer Systems Colloquium
4:15PM, Wednesday, May 13, 2009
HP Auditorium, Gates Computer Science Building B01
http://ee380.stanford.edu
Topic: Accelerating computation with FPGAs with a seismic computation example.
About the speaker:
Michael Flynn is now Professor Emeritus of EE at Stanford. He directed the Architecture and Arithmetic group in CSL for many years. He is now Senior Adviser and Board Chairman at Maxeler.



